MOSFET devices, which may operate at medium and high voltage, besides being used for executing several functions, for example, for DC/DC conversion, for the charging and for the protection of batteries, and inside lamps, are used in automotive applications. In the applications relative to this field, it also may be important to dissipate a minimum amount of heat, even if high currents are being drawn. For reaching high values of biasing inverted voltage BVdss of a planar MOSFET device, one may increase the thickness of its epitaxial layer and its resistivity. This implies the increase of the input resistance Rdson of the MOSFET device at the current flow through the device itself, and, in consequence, a greater amount of dissipated heat.
At present, n-channel MOSFET devices of medium and high voltage may be realized with different structures according to manufacturing needs. More in detail, the structure of a MOSFET device integrated on a semiconductor substrate may be conventionally of the planar type, or, alternatively, realized with a trench, or of the super-junction type, or also of the field-effect or field-plate type.
In a MOSFET device integrated on a semiconductor substrate, for example of silicon, the value of the resistance Rdson depends on the value of the breakdown voltage BVdss, according to the relation: Rdson˜BVdss2.5. In consequence, the value of the resistance Rdson also depends on the thickness and on the concentration of the epitaxial layer being grown on the silicon substrate.
To overcome this problem, MOSFET devices may be realized with the field-control-electrodes technique, or field plate, for eliminating the dependence of the resistance Rdson on the value of the breakdown voltage BVdss and, thus, on the thickness and on the concentration of the epitaxial layer. By way of example, FIG. 1 shows an enlarged view of a section of a MOSFET device 1 integrated on a semiconductor substrate 2 with a field-plate structure. The MOSFET device 1 comprises an epitaxial layer 3 that is grown on the substrate 2 (Substrate) and constitutes the drain region of the device. The device 1 also comprises buried source regions 4 realized by making, in the epitaxial layer 3, a trench 5 and filling it, in a first step, with a dielectric material 6, for example a thick oxide, that remains on the walls of the trench 5 and, in a second step, with a conductive material, for example through a first deposition of a polysilicon layer. This polysilicon layer is then subjected to masking and etching with consequent retrogression of the thick oxide layer 6. A gate oxide layer 7 and a second polysilicon layer are then realized, and then subjected to photomasking and etching. Within the epitaxial layer 3, in correspondence with the buried source regions 4, gate regions 8 (Gate electrode) are then realized. Subsequently, in the epitaxial layer 3, through implantation of different doping species, body regions 9 are realized and, within these, source regions 10. As it is clear also from the structure shown in FIG. 2, these steps follow: —deposition of a dielectric layer 11 useful for sealing the structure; —realization of a trench or micro-trench 12 in the body 9 and source 10 regions; —covering of the micro-trench with a metallic layer (for example tungsten) 13 for creating the contact with the body 9 and source 10 regions; —formation, through metallization, of a drain contact region 14 (Drain metal) and of a source contact region 15 (Source metal).
In practice, the field-plate technique is based on the application to the buried source electrode 4 of a suitable external voltage, that produces, in the epitaxial layer 3, a depleting of majority carriers through field-effect. The epitaxial layer 3, behaving as an intrinsic semiconductor, may then sustain high inverse breakdown voltages BVdss and, as effect of the depleting of the carriers further to the modulation of the voltage on the buried source electrode 4, may have high dopant concentrations and low values of the resistance component Repy Rdson due to the resistance of the epitaxial layer.
Embodiments of the field-plate technique for the realization of MOSFET devices are described in the following U.S. patents and patent applications: U.S. Pat. No. 7,504,303, 2004/0089910, 2007/0296039, U.S. Pat. Nos. 7,005,351, 7,372,103, 7,482,654, 7,183,610, and 7,557,409, which are incorporated by reference.
However, known application of the field-plate technique may have the drawback of being quite expensive and disadvantageous as to the electric performances of the device. For example, for the realization of the gate region, it may be necessary to execute two separate steps of deposition of polysilicon layers and, due to this, the insertion of a parasitic capacitance C may also be created between the buried source region 4 and the gate region 8, as shown in FIG. 2.